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Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog)
By
Volnei A. Pedroni
Volnei A. Pedroni
Volnei A. Pedroni is Professor of Electrical Engineering at Caltech and UTFPR (Federal University of Technolgy–Paraná), Brazil. He is the author of
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The MIT Press
ISBN electronic:
9780262319096
In Special Collection:
CogNet
Publication date:
2013
Citation
2013. "Design Steps and Classical Mistakes", Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog), Volnei A. Pedroni
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