MIT Press

The main features of these neuromorphic systems are shown in Table 5. Note that for the execution of the network, only the learning approaches that are implemented on-chip to run online are reviewed in this table.

Table 5:

Summary of Neuromorphic Systems Implementations.

Platform	Electronics	Technology (nm)	Chip Area (mm $^{2}$ ⁠)	On-Chip Learning	Neuron Model	Neuron Number (chip)	Synapse Model	Synapse Number (chip)	Online Learning	Power
BrainScaleS	Analog/digital	ASIC-CMOS 180	50	Yes (STDP)	Adaptive exponential IF	512	Spiking 4-bit digital	100 K	Yes	2 kW per module (peak)
TrueNorth	Digital	ASIC-CMOS 28	430	No	LIF	1 million	Binary, 4 modulators	256 M	No	65 mW (per chip)
SpiNNaker	Digital	ASIC-CMOS 130 nm	102	Yes (synaptic plasticity rules)	LIF, IZH, HH	16,000	Programmable	16 M	Yes	1 W (per chip)
Neurogrid	Analog/digital	ASIC-CMOS 180	168	No	Adaptive quadratic IF	65,000	Shared dendrite	100 M	Yes	2.7 W
Loihi	Digital	ASIC-CMOS 14 nm	60	Yes (with plasticity rule)	Adaptive LIF	131,000	N/A	126 M	Yes	$\approx$ ⁠.45 W

Platform	Electronics	Technology (nm)	Chip Area (mm $^{2}$ ⁠)	On-Chip Learning	Neuron Model	Neuron Number (chip)	Synapse Model	Synapse Number (chip)	Online Learning	Power
BrainScaleS	Analog/digital	ASIC-CMOS 180	50	Yes (STDP)	Adaptive exponential IF	512	Spiking 4-bit digital	100 K	Yes	2 kW per module (peak)
TrueNorth	Digital	ASIC-CMOS 28	430	No	LIF	1 million	Binary, 4 modulators	256 M	No	65 mW (per chip)
SpiNNaker	Digital	ASIC-CMOS 130 nm	102	Yes (synaptic plasticity rules)	LIF, IZH, HH	16,000	Programmable	16 M	Yes	1 W (per chip)
Neurogrid	Analog/digital	ASIC-CMOS 180	168	No	Adaptive quadratic IF	65,000	Shared dendrite	100 M	Yes	2.7 W
Loihi	Digital	ASIC-CMOS 14 nm	60	Yes (with plasticity rule)	Adaptive LIF	131,000	N/A	126 M	Yes	$\approx$ ⁠.45 W

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